In a semiconductor memory such as a DRAM, memory cells arranged in a matrix form are coupled to one of complementary bit lines. In a test process of this type of semiconductor memory, for example, for detecting a leak failure or the like between memory cells or bit lines, data of arbitrary logic (test pattern) is written in memory cells MC. In another way, a test pattern which easily causes noise is written in memory cells for evaluating an operation margin. Here, for performing a test without generating a complicated test pattern, there is proposed an approach to write a data signal supplied to one data terminal in the memory cells corresponding to another data terminal depending on an address signal supplied as a test pattern (see, for example, Japanese Laid-open Patent Publication No. H7-130197). Alternatively, there is proposed an approach to assign the bit numbers of plural data terminals to bits of an address signal during a test mode, and invert the logic of a data signal supplied to the data terminals depending on an address signal supplied as a test pattern (see, for example, Japanese Laid-open Patent Publication No. 2002-319299).
In recent years, accompanying miniaturization of transistor structures, there is a tendency that the gap between a contact of a voltage line supplied to a sense amplifier or a voltage line supplied to a precharge circuit and a bit line becomes narrow. Accordingly, leak failures are more liable to occur between these wirings.